Top layers of metal for high performance IC&#39;s

ABSTRACT

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

This application is a continuation of application Ser. No. 11/230,102,filed on Sep. 19, 2005, now pending, which is a continuation ofapplication Ser. No. 11/121,477, filed on May 4, 2005, now pending,which is a continuation of application Ser. No. 10/389,543, filed onMar. 14, 2003, now U.S. Pat. No. 6,965,165, which is a division ofapplication Ser. No. 09/972,639, filed on Oct. 9, 2001, now U.S. Pat.No. 6,657,310, which is a division of application Ser. No. 09/251,183,filed on Feb. 17, 1999, now U.S. Pat. No. 6,383,916, which is acontinuation-in-part of application Ser. No. 09/216,791, filed on Dec.21, 1998, now abandoned.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The invention relates to the manufacturing of high performanceIntegrated Circuit (IC's), and more specifically to methods of achievinghigh performance of the Integrated Circuits by reducing the parasiticcapacitance and resistance of inter-connecting wiring on a chip.

(2) Description of the Prior Art

When the geometric dimensions of the Integrated Circuits are scaleddown, the cost per die is decreased while some aspects of performanceare improved. The metal connections which connect the Integrated Circuitto other circuit or system components become of relative more importanceand have, with the further miniaturization of the IC, an increasinglynegative impact on the circuit performance. The parasitic capacitanceand resistance of the metal interconnections increase, which degradesthe chip performance significantly. Of most concern in this respect isthe voltage drop along the power and ground buses and the RC delay ofthe critical signal paths. Attempts to reduce the resistance by usingwider metal lines result in higher capacitance of these wires.

To solve this problem, the approach has been taken to develop lowresistance metal (such as copper) for the wires while low dielectricmaterials are used in between signal lines. Increased Input-Output (IO)combined with increased demands for high performance IC's has led to thedevelopment of Flip Chip Packages. Flip-chip technology fabricates bumps(typically Pb/Sn solders) on Al pads on chip and interconnect the bumpsdirectly to the package media, which are usually ceramic or plasticbased. The flip-chip is bonded face down to the package medium throughthe shortest path. These technologies can be applied not only tosingle-chip packaging, but also to higher or integrated levels ofpackaging in which the packages are larger and to more sophisticatedsubstrates that accommodate several chips to form larger functionalunits.

The flip-chip technique, using an area array, has the advantage ofachieving the highest density of interconnection to the device and avery low inductance interconnection to the package. However,pre-testability, post-bonding visual inspection, and TCE (TemperatureCoefficient of Expansion) matching to avoid solder bump fatigue arestill challenges. In mounting several packages together, such as surfacemounting a ceramic package to a plastic board, the TCE mismatch cancause a large thermal stress on the solder-lead joints that can lead tojoint breakage caused by solder fatigue from temperature cyclingoperations.

U.S. Pat. No. 5,212,403 (Nakanishi) shows a method of forming wiringconnections both inside and outside (in a wiring substrate over thechip) for a logic circuit depending on the length of the wireconnections.

U.S. Pat. No. 5,501,006 (Gehman, Jr. et al.) shows a structure with aninsulating layer between the integrated circuit (IC) and the wiringsubstrate. A distribution lead connects the bonding pads of the IC tothe bonding pads of the substrate.

U.S. Pat. No. 5,055,907 (Jacobs) discloses an extended integrationsemiconductor structure that allows manufacturers to integrate circuitrybeyond the chip boundaries by forming a thin film multi-layer wiringdecal on the support substrate and over the chip. However, thisreference differs from the invention.

U.S. Pat. No. 5,106,461 (Volfson et al.) teaches a multi layerinterconnect structure of alternating polyimide (dielectric) and metallayers over an IC in a TAB structure.

U.S. Pat. No. 5,635,767 (Wenzel et al.) teaches a method for reducing RCdelay by a PBGA that separates multiple metal layers.

U.S. Pat. No. 5,686,764 (Fulcher) shows a flip chip substrate thatreduces RC delay by separating the power and I/O traces.

SUMMARY OF THE INVENTION

It is the primary objective of the present invention to improve theperformance of High Performance Integrated Circuits.

Another objective of the present invention is to reduce resistivevoltage drop of the power supply lines that connect the IC tosurrounding circuitry or circuit components.

Another objective of the present invention is to reduce the RC delayconstant of the signal paths of high performance IC's.

Yet another objective of the present invention is to facilitate theapplication of IC's of reduced size and increased circuit density.

Yet another objective of the present invention is to further facilitateand enhance the application of low resistor conductor metals.

Yet another objective of the present invention is to allow for increasedI/O pin count for the use of high performance IC's.

Yet another objective of the present invention is to simplify chipassembly by reducing the need for re-distribution of I/O chipconnections.

Yet another objective of the present invention is to facilitate theconnection of high-performance IC's to power buses.

Yet another objective of the present invention is to facilitate theconnection of high-performance IC's to clock distribution networks.

Yet another objective of the present invention is to reduce ICmanufacturing costs by allowing or facilitating the use of lessexpensive process equipment and by accommodating less strict applicationof clean room requirements, this as compared to sub-micron manufacturingrequirements.

Yet another objective of the present invention is to be a driving forceand stimulus for future system-on-chip designs since the presentinvention allows ready and cost effective interconnection betweenfunctional circuits that are positioned at relatively large distancesfrom each other on the chip.

Yet another objective of the present design is to form the basis for acomputer based routing tool that automatically routes interconnectionsthat exceed a pre-determined length in accordance with the type ofinterconnection that needs to be established.

The present invention adds one or more thick layers of dielectric andone or more layers of wide metal lines on top of the finished devicewafer. The thick layer of dielectric can, for example, be of polyimideor benzocyclobutene (BCB) with a thickness of over, for example, 3 um.The wide metal lines can, for instance, be of aluminum or electroplatedcopper. These layers of dielectric and metal lines can be used for powerbuses or power planes, clock distribution networks, critical signal,re-distribution of I/O pads for flip chip applications, and for longsignal paths.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a cross section of the interconnection scheme of thepresent invention.

FIG. 2 shows a cross section of the present invention in a more complexcircuit configuration.

FIG. 3 a shows the top view of a combination power and X-signal planeusing the present invention.

FIG. 3 b shows the top view of a combination power and Y-signal planeusing the present invention.

FIG. 4 shows the top view of solder bump arrangement using the presentinvention and is an expanded view of a portion of FIG. 5.

FIG. 5 shows the top view of an example of power/ground pads combinedwith signal pad using the present invention.

FIG. 6 shows a basic integrated circuit (IC) interconnect scheme of theinvention.

FIG. 7 shows an extension of the basic IC interconnect scheme by addingpower, ground and signal distribution capabilities.

FIG. 8 shows an approach of how to transition from sub-micron metal towide metal interconnects.

FIG. 9 shows detail regarding BGA device fan out using the invention.

FIG. 10 shows detail regarding BGA device pad relocation using theinvention.

FIG. 11 shows detail regarding the usage of common power, ground andsignal pads for BGA devices using the invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention teaches an Integrated Circuit structure where keyre-distribution and interconnection metal layers and dielectric layersare added over a conventional IC. These re-distribution andinterconnection layers allow for wider buses and reduce conventional RCdelay.

Referring now more specifically to FIG. 1, there is shown a crosssection of one implementation of the present invention. A siliconsubstrate 1 has transistors and other devices, typically formed of polysilicon, covered by a dielectric layer 2 deposited over the devices andthe substrate. Layer 3 indicates the totality of metal layers anddielectric layers that are typically created on top of the device layer2. Points of contact 6, such as bonding pads known in the semiconductorart, are in the top surface of layers 3 and are part of layer 3. Thesepoints of contact 6 are points within the IC arrangement that need to befurther connected to surrounding circuitry, that is to power lines or tosignal lines. A passivation layer 4, formed of for example siliconnitride, is deposited on top of layer 3, as is known in the art forprotecting underlying layers from moisture, contamination, etc.

The key steps of the invention begin with the deposition of a thicklayer 5 of polyimide is deposited. A pattern 7 is exposed and etchedthrough the polyimide layer 5 and the passivation layer 4 where thepattern 7 is the same as the pattern of the contact points 6. This opensthe contact points 6 up to the surface 8 of the polyimide layer 5.

Electrical contact with the contact points 6 can now be established byfilling the openings 7 with a conductor. The tops 9 of this metalconductor can now be used for connection of the IC to its environment,and for further integration into the surrounding electrical circuitry.Pads 10, 11 and 12 are formed on top of the top 9 of the metalconductors 7; these pads can be of any design in width and thickness toaccommodate specific circuit design requirements. A larger size pad can,for instance, be used as a flip chip pad. A somewhat smaller in size padcan be used for power distribution or as a ground or signal bus. Thefollowing connections can, for instance, be made to the pads shown inFIG. 1: pad 10 can serve as a flip chip pad, pad 11 can serve as a flipchip pad or can be connected to electrical power or to electrical groundor to an electrical signal bus, pad 12 can also serve as a flip chippad. There is no connection between the size of the pads shown in FIG. 1and the suggested possible electrical connections for which this pad canbe used. Pad size and the standard rules and restrictions of electricalcircuit design determine the electrical connections to which a given padlends itself.

The following comments relate to the size and the number of the contactpoints 6, FIG. 1. Because these contact points 6 are located on top of athin dielectric (layer 3, FIG. 1) the pad size cannot be too large sincea large pad size brings with it a large capacitance. In addition, alarge pad size will interfere with the routing capability of that layerof metal. It is therefore preferred to keep the size of the pad 6 small.The size of pad 6 is however also directly related with the aspect ratioof via 7. An aspect ratio of about 5 is acceptable for the considerationof via etching and via filling. Based on these considerations, the sizeof the contact pad 6 can be in the order of 0.3 μm to 5.0 μm, the exactsize being dependent on the thickness of layers 4 and 5. The contactpoints 6 can comprise any appropriate contact material, such as but notlimited to tungsten, copper (electroplated or electroless), aluminum,polysilicon, or the like.

The present invention does not impose a limitation on the number ofcontact pads that can be included in the design; this number isdependent on package design requirements. Layer 4 in FIG. 1 can be atypical IC passivation layer.

The most frequently used passivation layer in the present state of theart is plasma enhanced CVD (PECVD) oxide and nitride. In creating layer4, a layer of between about 0.15 and 2.0 μm PECVD oxide is depositedfirst followed by a layer of between about 0.5 and 2.0 μm, andpreferably approximately 0.7 μm nitride. Passivation layer 4 is veryimportant because it protects the device wafer from moisture and foreignion contamination. The positioning of this layer between the sub-micronprocess (of the integrated circuit) and the tens-micron process (of theinterconnecting metallization structure) is of critical importance sinceit allows for a cheaper process that possibly has less stringent cleanroom requirements for the process of creating the interconnectingmetallization structure.

Layer 5 is a thick polymer dielectric layer (for example polyimide) thathas a thickness in excess of 2 μm (after curing) The range of polyimidethickness can vary from 2 μm to 30 μm dependent on electrical designrequirements.

For the deposition of layer 5 the Hitachi-Dupont polyimide HD 2732 or2734 can, for example, be used. The polyimide can be spin-on coated andcured. After spin-on coating, the polyimide will be cured at betweenapproximately 250 and 450 degrees C., preferably at 400 degrees C., forbetween approximately 0.5 and 1.5 hours, preferably for 1 hour, in avacuum or nitrogen ambient. For thicker polyimide, the polyimide filmcan be multiple coated and cured.

Another material that can be used to create layer 5 is the polymerbenzocyclobutene (BCB). This polymer is at this time commerciallyproduced by for instance Dow Chemical and has recently gained acceptanceto be used instead of typical polyimide application.

The dimensions of opening 7 have previously been discussed. Thedimension of the opening together with the dielectric thicknessdetermines the aspect ratio of the opening. The aspect ratio challengesthe via etch process and the metal filling capability. This leads to adiameter for opening 7 in the range of approximately 0.5 μm to 3.0 μmwhile the height for opening 7 can be in the range of approximately 3 μmto 20 μm. The aspect ratio of opening 7 is designed such that filling ofthe via with metal can be accomplished. The via can be filled with CVDmetal such as CVD tungsten or CVD copper, with electro-less nickel, witha damascene metal filling process, with electroplating copper, withsputtering aluminum, etc.

It must be noted that the use of polyimide films as inter-leveldielectrics has been pursued as a technique for providing partialplanarization of a dielectric surface. Polyimides offer the followingcharacteristics for such applications:

-   -   they produce surfaces in which the step heights of underlying        features are reduced, and step slopes are gentle and smooth.    -   they are available to fill small openings without producing the        voids that occur when low-temperature CVD oxide films are        deposited.    -   the cured polyimide films can tolerate temperatures of up to 500        degrees C. without degradation of their dielectric film        characteristics.    -   polyimide films have dielectric breakdowns, which are only        slightly lower than that of SiO₂.    -   the dielectric constant of polyimides is smaller than that of        silicon nitride and of SiO₂.    -   the process used to deposit and pattern polyimide films is        relatively simple.

For all of the above characteristics, polyimides are used andrecommended within the scope of the present invention.

FIG. 2 shows how the present invention as indicated in FIG. 1 can befurther extended to include multiple layers of polyimide and, in sodoing, can be adapted to a larger variety of applications. The lowerlevel build up of this cross section is identical to the build up shownin FIG. 1 with a silicon wafer 1, the poly silicon layer 2, the metaland dielectric combined layer 3, the passivation layer 4, the polyimidelayer 5 and the pads 10 deposited on top of layer 5. The function of thestructure that has been described in FIG. 1 can be further extended bydepositing another layer of polyimide 14 on top of the previouslydeposited layer 5 and overlaying the pads 10. Selective etching andmetal deposition can further create contact points 12. These contactpoints 12 can be connected with pads 10 as shown by connector 13.Depositing pads 12 on top of layer 14 can thus further extend thisprocess. These pads 12 can be further customized to a particularapplication, the indicated extension of multiple layers of polyimidesgreatly enhances the flexibility and usefulness of the presentinvention. Additional alternating layers of polyimide and metal linesand/or power or ground planes may be added above layers 12 and 16, asneeded. Dielectric layers 14 and 16 can be formed as described abovewith reference to FIG. 1 for the dielectric layer 5.

FIGS. 3 a and 3 b show a top view of one possible use of the presentinvention. Interconnecting a number of pads 32 that have been created asdescribed creates signal lines 30. Additional contact points such aspoint 34 can allow signal lines to pass vertically between layers. Thevarious contact points can, for instance, be created within the surfaceof a power plane or ground plane 36. The layers within theinterconnecting metallization structure of the present invention cancontain signal interconnections in the X-direction, signalinterconnections in the Y-direction, signal interconnections between Xand or Y directions, interconnections to and/or within power and/orground buses. The present invention further teaches the interconnectionof signal lines, power and ground buses between the connected IC's andthe top of the metallization system of the present invention.

FIG. 3 a shows signal lines formed in the X-direction.

FIG. 3 b shows signal lines formed in the Y-direction.

FIG. 4 presents yet another application of the present invention. Shownin FIG. 4 is an exploded view of a part of FIG. 5 that presents an areaarray I/O distribution. FIG. 4 shows pads 41 (on which solder bumps canbe created) and an example of a layout of the redistribution of theperipheral pads 41′. The exploded view of FIG. 4 is taken along the line2-2′ shown in FIG. 5; the redistribution of the peripheral pads 41′ (seeFIG. 4) is, for clarity of overview, not shown in FIG. 5. The power orground connections can be made to any point that is required on thebottom device. Furthermore, the power and ground planes can be connectedto the power and ground planes of the package substrates. FIG. 4 showsan example of how to use the topmost metal layer to redistribute theperipheral pads 41′ to become area array pads 41. The solder bumps canthen be created on pads 41.

FIG. 5 shows the top surface of a plane that contains a design patternof a combination of power or ground pads 52 and signal pads 54. FIG. 5shows the pad openings in the top dielectric layer. It is to be notedthat the ground/power pads 52 are heavier and larger in design relativeto the signal pads 54. The present invention ideally lends itself tomeeting these differences in design, as they are required within the artof chip and high performance circuit design. The number of power orground pads 52 shown in FIG. 5 can be reduced if there are power and/orground planes within the chip 53. From this it is clear that the packagenumber of I/O's can be reduced within the scope of the present inventionwhich leads to a reduction of the package cost by eliminating commonsignal/power/ground connections within the package. For instance, a 470I/O count on a BGA chip can, within the scope of the present invention,be reduced to a 256 I/O count using the present invention. This resultsin considerable savings for the overall package.

FIG. 6 shows a basic design advantage of the invention. This advantageallows for the sub-micron or fine-lines, that run in the immediatevicinity of the metal layers 3 and the contact points 6, to be extendedin an upward direction 20 through metal interconnect 7′. This extensioncontinues in the direction 22 in the horizontal plane of the metalinterconnect 26 and comes back down in the downward direction 24 throughmetal interconnect 7″. The functions and constructs of the passivationlayer 4 and the insulating layer 5 remain as previously highlightedunder FIG. 1. This basic design advantage of the invention is to“elevate” or “fan-out” the fine-line interconnects and to remove theseinterconnects from the micron and sub-micron level to a metalinterconnect level that has considerably larger dimensions and istherefore characterized by smaller resistance and capacitance and iseasier and more cost effective to manufacture. This aspect of theinvention does not include any aspect of conducting line re-distributionand therefore has an inherent quality of simplicity. It thereforefurther adds to the importance of the invention in that it makes micronand sub-micron wiring accessible at a wide-metal level. Theinterconnections 7′ and 7″ interconnect the fine-level metal by going upthrough the passivation and polymer or polyimide dielectric layers,traverses over a distance on the wide-metal level and continues bydescending from the wide-metal level back down to the fine-metal levelby again traversing down through the passivation and polymer orpolyimide dielectric layers. The extensions that are in this manneraccomplished need not to be limited to extending fine-metal interconnectpoints 6 of any particular type, such as signal or power or ground, withwide metal line 26. The laws of physics and electronics will imposelimitations, if any, as to what type of interconnect can by establishedin this manner where limiting factors will be the conventional limitingfactors of resistance, propagation delay, RC constants and others. Theupper metallization structure over the passivation layer 4 may compriseany appropriate contact material, such as but not limited to tungsten,chromium, copper (electroplated or electroless), aluminum, polysilicon,or the like. The upper metallization structure over the passivationlayer 4 and over the contact points 6 can be formed using a processcomprising an electroplating process, a sputtering process, anelectroless-plating process, or a damascene process. Where the inventionis of importance is that the invention provides much broader latitude inbeing able to apply these laws and, in so doing, provides a considerablyextended scope of the application and use of Integrated Circuits and theadaptation of these circuits to a wide-metal environment. The uppermetallization structure may have multiple metal layers and multipledielectric layers as depicted in FIG. 2. The upper metallizationstructure may comprise multiple metal traces and a metal plane, such asa power plane or ground plane, enclosing the metal traces as shown inFIGS. 3 a and 3 b.

FIG. 7 shows how the basic interconnect aspect of the invention canfurther be extended to now not only elevate the fine-metal to the planeof the wide-metal but to also add power, ground and signal distributioninterconnects of power, ground and signal planes at the wide-metallevel. The wide-metal interconnect 26 of FIG. 6 is now extended tofurther include an interconnection with the via 21. In typical ICdesign, some pads may not be positioned in a location from which easyfan-out can be accomplished to a location that is required for the nextstep of circuit assembly. In those cases, the BGA substrate requiresadditional layers in the package construction in order to accomplish therequired fan-out. The invention teaches an approach that makesadditional layers in the assembling of an IC feasible while not undulyincreasing the cost of creating such a multi-layer interface. Ballformation 28 on the surface of interconnect 23 indicates how theinvention replaces part of the conventional BGA interconnect function,the solder bump provides for flip chip assembly. This interconnect 28now connects the BGA device with surrounding circuitry at the wide-metallevel as opposed to previous interconnects of the BGA device at thefine-metal level. The wide-metal interconnect of the BGA has obviousadvantages of cost of manufacturing and improved BGA device performance.By being able to readily extend the wide-metal dimensions it alsobecomes possible to interconnect power, ground and signal lines at awide-metal level thereby reducing the cost and complexity of performingthis function at the fine-metal level. The indication of 28 as a balldoes not imply that the invention is limited to solder bumps for makinginterconnects. The invention is equally applicable to wirebonding formaking circuit interconnects.

FIG. 8 further shows a cross section wherein the previous linearconstruction of the metal interconnection running through thepassivation layer and the insulation layer is now conical in form. Thesub-micron metal layer 60 is covered with a passivation layer 62, alayer 64 of polyimide or polymer is deposited over the passivation layer62. The wide metal level 66 is formed on the surface of layer 64. Thevia 70 is shown as having sloping sides, these sloping sides can beachieved by controlling the photolithography process that is used tocreated the via 70. The etching of the polyimide or polymer can forinstance be done under an angle of about 75 degrees with the followingcuring being done under an angle of 45 degrees. Also, a photosensitivepolyimide or polymer can be used, the cone shape of the via 70 can inthat case be achieved by variation of exposure combined with time ofexposure combined with angle of exposure. Where non-photosensitivepolymer or polyimide is used, a wet etch can be applied that has agradated faster and longer time etch as the top of the via 70 is beingapproached. The layer of wide-metal pad 68 is deposited on the surfaceof the polymer or polyimide layer 64, the wide-metal pad deposition 68mates with the top surface of the via 70 and is centered on top of thissurface.

FIGS. 9 through 11 show further detail to demonstrate the concepts ofBGA chip ball fan-out, pad relocation and the creation of common ground,power and signal pads. The concept of pad relocation, fan-out, padaddition or pad reduction can be realized by forming the wide and thickmetal interconnection scheme over the passivation layer described inthis invention, to replace the function of BGA substrate 130.

FIG. 9 shows a cross section 100 of a BGA chip, five balls 101 through105 are also shown. By using the BGA substrate 106 and the wiring 107within the substrate 106, it is clear that ball 101 can be repositionedto location 111, ball 102 to location 112, etc. for the remaining solderbumps 103 through 105. It is clear that the separation of contact points111 through 115 is considerably larger than the separation of theoriginal solder bumps 101 through 105. The BGA substrate 106 is thesubject of the invention, this substrate allows for spreading thedistance between the contact points or balls of the BGA device to aconsiderable degree.

FIG. 10 shows the concept of pad relocation. BGA pad 120 connects to anyof the contact balls 101 through 105. By using the BGA substrate 130 andthe wiring 131 that is provided within the substrate, it is clear thatthe BGA pads can be arranged in a different and arbitrary sequence thatis required for further circuit design or packaging. For instancecontact point 101, which is on the far left side of the BGA device 100,is re-routed to location 122 which is on the second far right of the BGAsubstrate 130. The re-arrangements of the other BGA solder bumps canreadily be learned from following the wiring 131 within the substrate131 and by tracing from solder bump to one of the contact points 122through 125 of the BGA substrate.

FIG. 11 shows the interconnecting of BGA device solder bumps into commonpower, ground or signal pads. The BGA chip 100 is again shown with fivesolder bumps 101 through 105. The BGA substrate 130 contains a wiringscheme that contains in this example three wiring units, one for eachfor the power, ground and signal bumps of the BGA device. It is clearfrom FIG. 11 that wire arrangement 132 connects BGA device solder bumps101, 103 and 105 to interconnect point 138 of the BGA substrate 130. Itcan further be seen that BGA device solder bump 104 is connected tointerconnect point 140 of the BGA substrate by means of the wirearrangement 136, while BGA device solder bump 102 is connected tointerconnect point 142 of the BGA substrate by means of the wirearrangement 134. The number of pins required to interconnect the BGAdevice 100 is in this manner reduced from five to three. It is clearthat for more BGA device solder bumps, as is the case for an actual BGAdevice, the numeric effect of the indicated wiring arrangement isconsiderably more beneficial.

The concept of fan-out, pad relocation can be realized by forming thewide and thick metal interconnection scheme over the passivation layerdescribed in this invention, to replace the function of BGA substrate130. From FIGS. 9, 10 and 11 it can be seen that the extendedfunctionality and extended wiring ability that are provided by theinterconnect wiring schemes that are typically created in the BGAsubstrate 130 can be substituted by forming the wide and thick metalinterconnection scheme over the passivation layer, on device 100. Someof the methods and possibilities of interconnect line routing that canbe implemented using the method of the invention are highlighted in thefollowing paragraphs.

Fan-out capability can be provided by the invention, using the metalconductors within the openings through the insulating layer and throughthe passivation layer that connect electrical contact pads of the topmetallization structure with contact points of the interconnectingmetallization structure. Each of the electrical contact points of theinterconnecting metallization structure is connected directly andsequentially with at least one electrical contact point of the topmetallization structure. In a fan-out scheme, the distance betweenelectrical contact points of the top metallization structure is largerthan the distance between electrical contact points of theinterconnecting metallization structure by a measurable amount.

Alternatively, in a pad-addition scheme, the number of electricalcontact pads of the upper metallization structure can exceed the numberof contact points of the interconnecting metallization structure by aconsiderable amount. This provides an addition effect.

Pad relocation may also be accomplished by the method of the invention.Electrical contact points of the top metallization structure areconnected with the contact points of the interconnecting metallizationstructure, directly but not necessarily sequentially, thereby creating apad relocation effect. In this method, the distance between electricalcontact points of the top metallization structure is larger than thedistance between the electrical contact points of the interconnectingmetallization structure by a measurable amount. The positions of theelectrical contact points of the top metallization structure over thepassivation layer from a top view are different from that of the contactpoints of the interconnecting metallization structure exposed by theopenings in the passivation layer.

A reduction effect may also be accomplished by the method of theinvention, wherein common nodes are connected together. Electricalcontact points on a top surface of the top metallization structure areconnected with contact points of the interconnecting metallizationstructure exposed by the openings in the passivation layer, where fewercontact points are used in the top metallization structure, sincefunctionally equivalent contact points in the interconnectingmetallization structure are connected together. That is, the number ofcontact points for a particular electrical function among the electricalcontact points of the top metallization structure is smaller than thenumber of electrical contact points of the interconnecting metallizationstructure exposed by the passivation layer by a measurable amount.

Some of the advantages of the present invention are:

1) improved speed of the IC interconnections due to the use of widermetal lines (which results in lower resistance) and thicker dielectricsbetween the interconnecting lines (which results in lower capacitanceand reduced RC delay). The improved speed of the IC interconnectionsresults in improved performance of High Performance IC's.

2) an inexpensive manufacturing process since there is no need forexpensive equipment that is typically used in sub-micron IC fabrication;there is also no need for the extreme clean room facilities that aretypically required for sub-micron manufacturing.

3) reduced packaging costs due to the elimination of the need forredundant I/O and multiple power and ground connection points that areneeded in a typical IC packaging.

4) IC's of reduced size can be packaged and inter-connected with othercircuit or system components without limiting the performance of theIC's.

5) since dependence on ultra-fine wiring is reduced, the use of lowresistance conductor wires is facilitated.

6) structures containing more complicated IC's can be created becausethe invention allows for increased I/O pin count.

7) more complicated IC's can be created without the need for asignificant increase in re-distribution of package I/O connections.

8) power buses and clock distribution networks are easier to integratewithin the design of IC's.

9) future system-on-chip designs will benefit from the present inventionsince it allows ready and cost effective interconnection betweenfunctional circuits that are positioned at relatively large distancesfrom each other on the chip.

10) form the basis for a computer based routing tool that automaticallyroutes interconnections that exceed a pre-determined length inaccordance with the type of interconnection that needs to beestablished.

11) provide a means to standardize BGA packaging.

12) be applicable to both solder bumps and wirebonding for makingfurther circuit interconnects.

13) provide a means for BGA device solder bump fan-out therebyfacilitating the packing and design of BGA devices.

14) provide a means for BGA device pad relocation thereby providingincreased flexibility for the packing and design of BGA devices.

15) provide a means for common BGA device power, ground and signal linesthereby reducing the number of pins required to interconnect the BGAdevice with the surrounding circuits.

16) provide a means for more relaxed design rules in designing circuitvias by the application of sloped vias.

17) provide the means for extending a fine-wire interconnect scheme to awide-wire interconnect scheme without the need to apply a passivationlayer over the surface of the fine-wire structure.

Although the preferred embodiment of the present invention has beenillustrated, and that form has been described in detail, it will bereadily understood by those skilled in the art that variousmodifications may be made therein without departing from the spirit ofthe invention or from the scope of the appended claims.

1. A method for fabricating an integrated circuit chip comprising:providing a silicon substrate, multiple devices in and on said siliconsubstrate, a first dielectric layer over said silicon substrate, a firstmetallization structure over said first dielectric layer and connectedto said multiple devices, said first metallization structure comprisinga first metal layer and a second metal layer over said first metallayer, a second dielectric layer between said first and second metallayers, a passivation layer over said first metallization structure andover said first and second dielectric layers, said passivation layercomprising a topmost nitride layer of said integrated circuit chip and atopmost oxide layer of said integrated circuit chip, and a polymer layeron said passivation layer, a first opening in said passivation layer andin said polymer layer exposing a first pad of said first metallizationstructure, and a second opening in said passivation layer and in saidpolymer layer exposing a second pad of said first metallizationstructure, wherein said polymer layer has a thickness between 2 and 30microns; and forming a second metallization structure over said polymerlayer and over said first and second pads, wherein said first pad isconnected to said second pad through said second metallizationstructure.
 2. The method of claim 1, wherein said forming said secondmetallization structure comprises an electroplating process.
 3. Themethod of claim 1, wherein said forming said second metallizationstructure comprises a copper electroplating process.
 4. The method ofclaim 1, wherein said forming said second metallization structurecomprises a sputtering process.
 5. The method of claim 1, wherein saidforming said second metallization structure comprises an aluminumsputtering process.
 6. The method of claim 1, wherein said forming saidsecond metallization structure comprises an electroless plating process.7. The method of claim 1, wherein said forming said second metallizationstructure comprises a nickel forming process.
 8. The method of claim 1,wherein said providing said polymer layer comprises forming said polymerlayer on said passivation layer using a process comprising coating andcuring.
 9. The method of claim 1, wherein said providing said polymerlayer comprises forming photosensitive polyimide on said passivationlayer.
 10. A method for fabricating an integrated circuit chipcomprising: providing a silicon substrate, multiple devices in and onsaid silicon substrate, a first dielectric layer over said siliconsubstrate, a first metallization structure over said first dielectriclayer and connected to said multiple devices, said first metallizationstructure comprising a first metal layer and a second metal layer oversaid first metal layer, a second dielectric layer between said first andsecond metal layers, and a passivation layer over said firstmetallization structure and over said first and second dielectriclayers, wherein said passivation layer comprises a topmost nitride layerof said integrated circuit chip and a topmost oxide layer of saidintegrated circuit chip; forming a polymer layer on said passivationlayer; after said forming said polymer layer, forming an opening in saidpassivation layer and in said polymer layer, exposing a pad of saidfirst metallization structure; and after said forming said opening,forming a second metallization structure over said pad and over saidpolymer layer.
 11. The method of claim 10, wherein said forming saidsecond metallization structure comprises an electroplating process. 12.The method of claim 10, wherein said forming said second metallizationstructure comprises a copper electroplating process.
 13. The method ofclaim 10, wherein said forming said second metallization structurecomprises a sputtering process.
 14. The method of claim 10, wherein saidforming said second metallization structure comprises an aluminumsputtering process.
 15. The method of claim 10, wherein said formingsaid second metallization structure comprises an electroless platingprocess.
 16. The method of claim 10, wherein said forming said secondmetallization structure comprises a nickel forming process.
 17. Themethod of claim 10, wherein said forming said polymer layer comprisescoating and curing.
 18. The method of claim 10, wherein said formingsaid polymer layer comprises forming photosensitive polyimide on saidpassivation layer.
 19. The method of claim 10, wherein said forming saidopening comprises a photolithography process.
 20. The method of claim10, wherein said forming said opening comprises an etching process. 21.A method for fabricating an integrated circuit chip comprising:providing a silicon substrate, multiple devices in and on said siliconsubstrate, a first dielectric layer over said silicon substrate, a firstmetallization structure over said first dielectric layer and connectedto said multiple devices, said first metallization structure comprisinga first metal layer and a second metal layer over said first metallayer, a second dielectric layer between said first and second metallayers, and a passivation layer over said first metallization structureand over said first and second dielectric layers, wherein saidpassivation layer comprises a topmost nitride layer of said integratedcircuit chip and a topmost oxide layer of said integrated circuit chip;forming an insulating layer over said passivation layer, wherein saidforming said insulating layer comprises forming a photosensitive polymerlayer on said passivation layer and forming a first opening and a secondopening in said photosensitive polymer layer using a process comprisingexposure; and forming a second metallization structure comprising afirst portion in said first opening, a second portion in said secondopening and a metal interconnect on said insulating layer, wherein saidfirst portion is connected to said second portion through said metalinterconnect.
 22. The method of claim 21, wherein said forming saidsecond metallization structure comprises an electroplating process. 23.The method of claim 21, wherein said forming said second metallizationstructure comprises a copper electroplating process.
 24. The method ofclaim 21, wherein said forming said second metallization structurecomprises a sputtering process.
 25. The method of claim 21, wherein saidforming said second metallization structure comprises an aluminumsputtering process.
 26. The method of claim 21, wherein said formingsaid second metallization structure comprises an electroless platingprocess.
 27. The method of claim 21, wherein said forming said secondmetallization structure comprises a nickel forming process.